The present invention relates to field effect transistors (FET's) on semiconductor substrates, such as GaAs-MESFET or HEMT.
In attempting to optimize symmetrically constructed FET's, two conflicting requirements, which are in part mutually exclusive, must be resolved. One requirement is that an optimally low source resistance be provided. The other requirement is the need for a moderate drain implantation, referred to as a lightly doped drain (LDD). A compromise must be struck between these two conflicting requirements, as the former yields an optimally high transconductance and low noise, whereas the latter yields an optimally high breakdown voltage and high power. The conflict between these two requirements can only be avoided by asymmetrically designing the source region, or the drain region, with respect to the gate.
An additional requirement to be considered is the gate length; short gate lengths are necessary for optimum high-frequency performance. However, a short gate length usually produces a pronounced short-channel effect. Such an effect may be largely suppressed by an LDD region. However, the use of an LDD region to suppress the short-channel effect makes it difficult to simultaneously reduce the source resistance.
An FET having asymmetrical source of drain regions is described in T. Enoki, et al., "0.3-.mu.m Advanced SAINT FET's Having Asymmetric n.sup.+ -Layers for Ultra-High-Frequency GaAs MMIC's", IEEE Transactions on Electron Devices, Vol. 35, 18-24 (1988). The FET is manufactured by applying a resist mask having a T-shaped cross section to the gate region. The source and drain regions are manufactured by an oblique ion implantation. Portions of the surface not covered by the resist mask are covered with a layer of SiO.sub.2. The resist mask is then removed, and a self-aligning gate metallization is applied, the SiO.sub.2 layer serving as a masking layer.
An FET having asymmetrically doped source and drain regions is described in T. Kimura et al., "Asymmetric Implantation Self-alignment Technique for GaAs MESFETs", Japanese Journal of Applied Physics. Vol. 27, L1340-L1343 (1988). The FET is manufactured by first applying a high-temperature-resistant metal as a gate metallization. A germanium layer is subsequently applied surfaced-wide followed by a layer of resist. The source region is formed through an opening in the resist by etching a portion of the exposed germanium layer down to the gate of the metal. After erosion of the resist, a germanium layer having an opening in the source region remains. An ion implantation into the source region is achieved through this opening. After removing the germanium layer, a further ion implantation can be symmetrically applied to the source region and the drain region, followed by an annealing of the doping. The doping of the source region twice, results in an asymmetry between the source region and the drain region.
Another field effect transistor having asymmetrically designed source and drain regions, whose manufacture relies upon the use of a high-temperature-resistant metal for the gate metallization, is described in A. E. Geissberger, "A New Refractory Self-Aligned Gate Technology for GaAs Microwave Power FET's and MMIC's", IEEE Transactions on Electron Devices, Vol. 35, 615-622 (1988). A metallized gate layer is applied, followed by a strip of resist applied to one side, thereby allowing for an asymmetric doping of the metal. The gate metal is then asymmetrically disposed with respect to the source and drain regions.